Circuits become more vulnerable as technology evolves because transistors shrink (length, width and thickness). Negative Bias Temperature Instability (NBTI) is a failure that affects positive channel transistors (e.g., PMOS) when the voltage at a gate of the transistor is negative.
FIG. 1 illustrates an example memory cell 100. The memory cell 100 includes two inverters 110, 120 connected in a ring manner so that one of the inverters will always have a negative voltage (logic value “0”) for an input while the other has a positive voltage (logic value “1”) for an input. As the inverters 110, 120 include PMOS transistors 112, 122, one of the PMOS transistors will always have a negative voltage applied to the gate while the other has a positive voltage applied to the gate. Accordingly, at all times one of the PMOS transistors in the memory cell 100 will be degrading while the other is not.
The best case degradation happens when the value in each inverter is “0” for 50% of the time so that each of the PMOS transistors degrades the same. However, if the activity patterns of the memory cells do not produce such a result, one PMOS may degrade more then the other. Whenever one transistor fails, the piece of logic becomes useless. Activity patterns for the different cache-like structures show significant imbalance because some of the bits are “0” most of the time.